ASX-listed memory developer Weebit Nano (WBT) has achieved a key technical milestone in its development of discrete (standalone) non-volatile memory chips, demonstrating its first operational crossbar arrays that combine its ReRAM technology with a selector. Weebit achieved the milestone with its development partner CEA-Leti.
Discrete memory chips consist of large arrays of memory cells, from Megabit (Mb or one million bits) to multi-Gigabit (Gb, or one billion bits) in size. They therefore require very high densities to contain as much memory as possible on the same piece of silicon.
The 1T1R (one transistor one resistor) architecture used in embedded ReRAM arrays is not sufficient to support the large arrays of memory cells needed in discrete memory chips as the transistors are too big. For this reason, Weebit’s crossbar arrays were developed using a 1S1R (one selector one resistor) architecture that enables the high density needed for discrete chips. Such an architecture also allows Weebit’s arrays to be stacked in 3D layers so they can deliver even higher densities.
Weebit’s 1S1R crossbar ReRAM architecture has potential applications in storage class memory, persistent memory and as a NOR flash replacement. It is also ideal for AI architecture such as in-memory computing and neuromorphic computing.
Commenting on the company’s latest technology development milestone, CEO Coby Hanoch said, “Weebit Nano continues to make significant technical and commercial progress within the embedded sector – recently successfully scaling our ReRAM technology down to 28nm. Now, with the creation of our first kilobit crossbar arrays, which combine our ReRAM technology with CEA-Leti’s selector technology, we’re continuing our progress toward discrete memory solutions.
“Developing such a crossbar array is a very innovative process that requires significant research. As part of this work, we recently filed several new patents together with CEA-Leti, designed to further protect Weebit’s ReRAM intellectual property, with a focus on 1S1R architectures and selector cell programming.”
